Functional slack time computation of logic gate

Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an

Volumn 8, Issue 4, 2001, Pages 325-334

  Cheng, C H ^a   Tien, T K ^a   Shen, Y C ^a   Chang, S C ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

Functional false path; Non primitive path; Primitive path; Statically co sensitizable path; Statically sensitizable path

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; OPTIMIZATION; THEOREM PROVING; TIMING CIRCUITS;

NON-PRIMITIVE PATHS; SLACK TIME COMPUTATION; STATICALLY SENSITIZABLE PATH; TOPOLOGICAL CRITICAL PATH;

LOGIC GATES;

EID: 0035506684     PISSN: 10234462     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

1. Path sensitization in critical path problem
2. A new approach to solving false path problem in timing analysis
3. On determining sensitization criterion in an iterative gate sizing process
4. SIS: A system for sequential synthesis
5. Efficient algorithms for extracting the k most critical paths in timing analysis