Backside localization of current leakage faults using thermal laser stimulation

Microelectronics Reliability

Volumn 41, Issue 9-10, 2001, Pages 1539-1544

  Desplats, R ^a   Beaudoin, F ^a   Perdu, P ^a   Poirier, P ^b   Tremouilles, D ^c,d   Bafleur, M ^c   Lewis, D ^e  

^a CNES   (France)

^b UNIVERSITÉ DE CAEN   (France)

^c LAAS CNRS   (France)

^d ON SEMICONDUCTOR   (United States)

^e UNIVERSITÉ BORDEAUX 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS; INTEGRATED CIRCUITS; LASER APPLICATIONS; SEMICONDUCTING SILICON;

THERMAL LASER STIMULATION;

LEAKAGE CURRENTS;

EID: 0035456899     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00167-6     Document Type: Article

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5. Beaudoin F., Chauffleur X., Fradin J.P., Perdu P., Desplats R. and Lewis D. This conference.
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7. JEDEC STANDARD Test Method n° JESD22-Al 14-B, JEDEC Solid State Technology Association (2000).