ESD-induced circuit performance degradation in RFICs

Microelectronics Reliability

Volumn 41, Issue 9-10, 2001, Pages 1379-1383

  Gong, K ^a   Feng, H G ^a   Zhan, R Y ^a   Wang, A Z ^a  

^a Illinois Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC CLOCKS; ELECTRIC DISCHARGES; NOISE GENERATORS;

CIRCUIT PERFORMANCE DEGRADATION;

INTEGRATED CIRCUITS;

EID: 0035456682     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00144-5     Document Type: Article

References (5)

1. Narita, K., Horiguchi, Y., Fujii, T., and Nakamura, K., "A Novel on-Chip Electrostatic Discharge (ESD) Protection with Common Discharge Line for High-speed CMOS LSIs", IEEE Trans. Elec. Dev., Vol. 44 No.7,1997, pp.1124-1130.
2. Ker, M.-D., Chang, H., and Wu, C., "A Gate-Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ICs", IEEE J. Solid State Cir., Vol. 32, No. 1, 1997, pp.38-51.
3. Gong, K., "ESD Protection in Copper Interconnect and ESD-to-Circuit Performance Influences", MS Thesis, IIT, May 2001.
4. Wang, A. and Tsay, C., "On a Dual-Direction on-Chip Electrostatic Discharge Protection Structure", IEEE Tram. Elec. Dev., Vol. 48, No. 5, May 2001, pp.978-984.
5. A. Wang, "A New Design for Complete on-Chip ESD Protection", Proc. IEEE CICC, 2000, pp.87-90.