Modeling differential via holes

IEEE Transactions on Advanced Packaging

Volumn 24, Issue 3, 2001, Pages 357-363

  Laermans, Eric ^a,b   De Geest, Jan ^a,b   De Zutter, Daniël ^a,b   Olyslager, Frank ^a,b   Sercu, Stefaan ^c   Morlion, Danny ^c  

^a IEEE   (Belgium)

^b GHENT UNIVERSITY   (Belgium)

^c Fci'S hertogenbosch BV   (Netherlands)

Author keywords

Differential signals; Networks models; Signal integrity; Via holes

Indexed keywords

DIFFERENTIAL VIA HOLES; RETURN CURRENT;

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRONICS PACKAGING; INDUCTANCE; INTEGRAL EQUATIONS; MATHEMATICAL MODELS; PERMITTIVITY; PRINTED CIRCUIT DESIGN;

PRINTED CIRCUIT BOARDS;

EID: 0035421185     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.938303     Document Type: Article

References (20)

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2. Modeling differential via holes
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5. Rigorous and simplified models for the capacitance of a circularly symmetric via
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17. Least-square estimation of the equivalent circuit parameters of a via-hole from a TDR reflectogram, including on-board rise time and delay estimation
18. A new approach for the experimental circuit modeling of coupled interconnection structures based on causality
19. Fast capacitance extraction of general three-dimensional structures
20. New fast and accurate line parameter calculation of multiconductor transmission lines in multilayered media