Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 48, Issue 8, 2001, Pages 947-956

  Baldick, Ross ^a,b   Kahng, Andrew B ^c   Kennings, Andrew ^d   Markov, Igor L ^e  

^a IEEE   (United States)

^b The University of Texas at Austin   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d CYPRESS SEMICONDUCTOR   (United States)

^e UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Analytical; Approximation; Convex; Delay half perimeter; Large scale; Linear; Nonlinear; Timing driven; VLSI placement; Wirelength

Indexed keywords

PLACEMENT ALGORITHMS;

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; HEURISTIC METHODS; NUMERICAL METHODS; OPTIMIZATION; PIECEWISE LINEAR TECHNIQUES;

VLSI CIRCUITS;

EID: 0035417507     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.940185     Document Type: Article

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