1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 979-987

  Boni, Andrea ^a,b  

^a IEEE   (Italy)

^b UNIVERSITY OF PARMA   (Italy)

Author keywords

Back plane drivers; CMOS integrated circuits; Emitter coupled logic; High speed integrated circuits; Input output (I O)

Indexed keywords

BACK PLANE DRIVERS; HIGH SPEED INTEGRATED CIRCUITS; INPUT-OUTPUT INTERFACE CIRCUITS; POSITIVE EMITTER COUPLED LOGIC SYSTEMS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; FEEDBACK CONTROL; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SWITCHING CIRCUITS;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 0035368209     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924860     Document Type: Article

References (13)

1. National technology roadmap for semiconductors
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7. Semiconductor General Information
8. High-speed digital design
9. Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model
10. A 500-Mb/s 20-channel CMOS laser diode array driver for a parallel optical bus
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