Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 8, 1999, Pages 1074-1083

  Djahanshahi, Hormoz ^a   Hansen, Flemming ^b   Salama, C André T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

^b Vitesse Semiconductor Corporation   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA COMMUNICATION EQUIPMENT; INTERFACES (COMPUTER); LOGIC CIRCUITS; SIGNAL RECEIVERS; TRANSMITTERS;

DIFFERENTIAL OPEN DRAIN CIRCUIT; EMITTER COUPLED LOGIC; INPUT OUTPUT INTERFACE;

DIGITAL CIRCUITS;

EID: 0033169553     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.777105     Document Type: Article

References (7)

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2. S. Gogaert, M. Steyaert, and V. Peluso, "622 Mbit/s board-to-board link in 0.5 μm CMOS technology," in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, CA, May 1995, pp. 447-450.
3. B. Gunning, L. Yuan, T. Nguyen, and T Wong, "A CMOS low-voltage-swing transmission-line transceiver," in ISSCC Dig. Tech. Papers, 1992, pp. 58-59.
4. H. J. Shumacher, J. Dikken, and E. Seevinck, "CMOS subnanosecond true-ECL output buffer," IEEE J. Solid-State Circuits, vol. 25, pp. 150-154, Feb. 1990.
5. T. F. Knight, Jr., and A. Krymm, "A self-terminating low-voltage swing CMOS output driver," IEEE J. Solid-State Circuits, vol. 23, pp. 457-464, Apr. 1988.
6. M. S. J. Steyaert, W. Bijker, P. Vorenkamp, and J. Sevenhans, "ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHz digital ECL data transmission systems," IEEE J. Solid-State Circuits, vol. 26, pp. 18-24, Jan. 1991.
7. H. Djahanshahi, F. Hansen, and C. A. T. Salama, "Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling," in Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1999, pp. 601-604.