A technique for transparent fault injection and simulation in VHDL

Microelectronics Reliability

Volumn 41, Issue 6, 2001, Pages 797-804

  Zwolinski, Mark ^a  

^a UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK ANALYSIS;

TRANSPARENT FAULT INJECTION;

GATES (TRANSISTOR);

EID: 0035366632     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00039-7     Document Type: Article

References (6)

1. Functional fault simulation of VHDL gate level models
2. A fault injection technique for VHDL behavioural-level models
3. Protected Shared Variables in VHDL: IEEE Standard 1076a