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Computers and Electrical Engineering
Volumn 27, Issue 2, 2001, Pages 201-216
Practical and efficient approach to the constrained via minimization problem
Author keywords

[No Author keywords available]
Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; OPTIMIZATION;
EID: 0035342679     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0045-7906(00)00015-X     Document Type: Article
Times cited : (2)
References (12)
  • 1
    • 85050951333 scopus 로고
    • Wire routing by optimizing channel assignment within large apertures
    • Hashimoto A., Stevens J. Wire routing by optimizing channel assignment within large apertures. Proc. 8th Design Automation Workshop :1971;155-169.
    • (1971) Proc. 8th Design Automation Workshop , pp. 155-169
    • Hashimoto, A.1    Stevens, J.2
  • 2
    • 0020751273 scopus 로고
    • A graph-theoretic via minimization algorithm for two-layer PCBs
    • Chen R.W., Kajitani Y., Chan S.P. A graph-theoretic via minimization algorithm for two-layer PCBs. IEEE Trans. Circuits Systems. 30:(5):1983;284-299.
    • (1983) IEEE Trans. Circuits Systems , vol.30 , Issue.5 , pp. 284-299
    • Chen, R.W.1    Kajitani, Y.2    Chan, S.P.3
  • 4
    • 0021482729 scopus 로고
    • Optimal layer assignment for interconnect
    • Pinter R.Y. Optimal layer assignment for interconnect. J. VLSI Comp. Syst. 1:1984;123-137.
    • (1984) J. VLSI Comp. Syst. , vol.1 , pp. 123-137
    • Pinter, R.Y.1
  • 6
    • 0024612478 scopus 로고
    • A unified approach to the via minimization problem
    • Xiong X.M., Kuh E.S. A unified approach to the via minimization problem. IEEE Trans. Circuits Systems. 36:(2):1989;190-204.
    • (1989) IEEE Trans. Circuits Systems , vol.36 , Issue.2 , pp. 190-204
    • Xiong, X.M.1    Kuh, E.S.2
  • 7
    • 0041976452 scopus 로고
    • Constrained via minimization and signed hyergraph partitioning
    • Singapore: World Scienific
    • Shi C.J. Constrained via minimization and signed hyergraph partitioning. Algorithm aspects of VLSI layout. 1993;World Scienific, Singapore.
    • (1993) Algorithm Aspects of VLSI Layout
    • Shi, C.J.1
  • 8
    • 0023089597 scopus 로고
    • Efficient algorithms for layer assignment problem
    • Chang K.C., Du D.H. Efficient algorithms for layer assignment problem. IEEE Trans. on CAD. 6:(1):1987;67-78.
    • (1987) IEEE Trans. on CAD , vol.6 , Issue.1 , pp. 67-78
    • Chang, K.C.1    Du, D.H.2
  • 9
    • 0029306647 scopus 로고
    • , An efficient mutli-layer diagonal router for multi-terminal printed circuit boards
    • Mody K., Jayasumana A. , An efficient mutli-layer diagonal router for multi-terminal printed circuit boards. Computers Elect. Engng. 21:(3):1995;147-158.
    • (1995) Computers Elect. Engng. , vol.21 , Issue.3 , pp. 147-158
    • Mody, K.1    Jayasumana, A.2
  • 10
    • 0030215548 scopus 로고    scopus 로고
    • A neural network model for multilayer topological via minimization in a switchbox
    • Funabiki N., Nishikawa S. A neural network model for multilayer topological via minimization in a switchbox. IEEE trans. on CAD. 15:(8):1996;1012-1020.
    • (1996) IEEE Trans. on CAD , vol.15 , Issue.8 , pp. 1012-1020
    • Funabiki, N.1    Nishikawa, S.2
  • 11
    • 0020193343 scopus 로고
    • Plane-sweep algorithms for intersecting geometric figures
    • Nievergelt J., Preparata F.P. Plane-sweep algorithms for intersecting geometric figures. Commun. ACM. 25:(10):1982;739-747.
    • (1982) Commun. ACM , vol.25 , Issue.10 , pp. 739-747
    • Nievergelt, J.1    Preparata, F.P.2
  • 12
    • 26444479778 scopus 로고
    • Et. al., Optimization by simulated annealing
    • Kirckpatrick S. et. al., Optimization by simulated annealing. Science. 220:1983;671-680.
    • (1983) Science , vol.220 , pp. 671-680
    • Kirckpatrick, S.1

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.