A neural network model for multilayer topological via minimization in a switchbox

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 8, 1996, Pages 1012-1020

  Funabiki, Nobuo ^a   Nishikawa, Seishi ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; NEURAL NETWORKS; OPTIMIZATION; VLSI CIRCUITS;

MULTITERMINAL NETS; NEURAL NETWORK MODEL; SWITCHBOX; TOPOLOGICAL VIA MINIMIZATION PROBLEM; TWO-LAYER BURSTEINS SWITCHBOX;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030215548     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.511580     Document Type: Article

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