Testing the robustness of two-boundary control policies in semiconductor manufacturing

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 2, 1996, Pages 285-288

  Yan, Houmin ^a   Lou, Sheldon ^b   Sethi, Suresh ^c   Gardel, Anne ^d   Deosthali, Prabhat ^d  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b CALIFORNIA STATE UNIVERSITY   (United States)

^c UNIVERSITY OF TORONTO   (Canada)

^d HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONTROL THEORY; PRODUCTION CONTROL; ROBUSTNESS (CONTROL SYSTEMS); SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS;

CYCLE TIME; DEMAND VARIATION; MACHINE BREAKDOWNS; RANDOM INTERFERENCE; TWO BOUNDARY CONTROL POLICIES;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030150598     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.492825     Document Type: Article

References (15)

1. D. Y. Burman, J. Gurrola-Cal, A. Nozari, S. Sathaye, and J. P. Sitarik, "Performance analysis techniques for IC manufacturing line," AT&T Bell Labs. Tech. J., 1986.
2. H. Cheti, J. M. Harrison, A. Mandelbaum, A. van Ackere, and L. M. Wein, "Empirical evaluation of a queueing network model for semiconductor wafer fabrication," Oper. Res., vol. 36, pp. 202-215, 1988.
3. L. Cory, "Just-in-time approach to IC fabrication," Solid State Technol., pp. 177-179, May 1986.
4. J. E. Dayhoff and R. W. Atherton, "Simulation of VLSI manufacturing areas," VLSI Design, pp. 84-92, Dec. 1984.
5. C. R. Glassey and G. C. Resende, "Closed-loop job release control for VLSI circuit manufacturing," IEEE Trans. Semiconduct. Manufact., vol. 1, no. 1, pp. 36-46, 1988.
6. S. X. C. Lou and P. Kager, "A robust production control policy for VLSI wafer fabrication," IEEE Trans. Semiconduct. Manufact., vol. 2, no. 4, 1989.
7. S. X. C. Lou, H. Yan, S. Sethi, A. Gardel, and P. Deosthali, "Hub-centered production control of wafer fabrication," in Proc. Advanced Semi-Conductor Manufact. Conf. and Workshop, Danvers, MA, Sept. 1990.
8. S. C. H. Lu, D. Ramaswamy, and P. R. Kumar, "Efficient scheduling policies to reduce mean and variance of cycle time in semiconductor manufacturing plants," IEEE Trans. Semiconduct. Manufact., vol. 7, no. 8, pp. 374-388, 1994.
9. L. M. Martin-Vega, M. Pippin, E. Gerdon, and R. Burcham, "Applying just-in-time in a water fab: A case study," IEEE Trans. Semiconduct. Manufact., vol. 2, no. 1, 1989.
10. G. Van Ryzin, S. X. C. Lou, and S. B. Gershwin, "Production control for a tandem two-machine system," IIE Trans., vol. 25, no. 5, pp. 5-20, 1993.
11. S. Sethi and Q. Zhang, Hierarchical Decision Making in Stochastic Manufacturing Systems. Boston: Birkhäuser, 1994.
12. R. Uzsoy, C. Y. Lee, and L. A. Martin-Vega, "A review of production planning and scheduling models in the semiconductor industry, Part I: System characteristics, performance evaluation and production planning," IIE Trans. Scheduling and Logistics, vol. 24, pp. 47-61, 1992.
13. _, "A review of production planning and scheduling models in the semiconductor industry, Part II: Shop-floor control," IIE Trans. Scheduling and Logistics, vol. 26, no. 5, 1994.
14. L. M Wein, "Scheduling semiconductor wafer fabrication," IEEE Trans. on Semiconduct. Manufact., vol. 1, no. 3, 1988.
15. H. Yan, S. Lou, S. Sethi, A. Gardel, and P. Deosthali, "Testing the robustness of various production policies in semiconductor manufacturing," working paper, Univ. of Toronto, 1994.