Evaluations of 300 mm Si wafer performances for giga ULSI device processes

Microelectronic Engineering

Volumn 56, Issue 1-2, 2001, Pages 27-39

  Takahashi, Kenji ^a   Kawashima, Kenichi ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

Author keywords

300 mm silicon crystal; COP Contamination; Cost; Flatness; GOI; Particle; TDDB

Indexed keywords

CONTAMINATION; COSTS; EPITAXIAL GROWTH; PROCESS ENGINEERING; PRODUCTION ENGINEERING; PRODUCTIVITY; ULSI CIRCUITS;

LARGE-SCALE VOLUME PRODUCTIONS;

SILICON WAFERS;

EID: 0035341743     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00501-3     Document Type: Article

References (5)

1. H. Thuchikawa, Proc. SEMI Technology. Symp. 96, Chiba, 8 (1996).
2. H. Komiya, Symp. on VLSI Technol, Kyoto, 1 (1997).
3. National Technology Roadmap for Semiconductors (SIA) (1997, 1999).
4. H. Komiya, Symp. on VLSI Technology, Kyoto, 1 (1997).
5. S. Muraoka, Jpn. J. Appl. Phys. 66 (1997) 673.