Barrier and seed technologies for sub-0.10 μm copper chips

Semiconductor International

Volumn 24, Issue 5, 2001, Pages 107-114

  Chin, Barry L ^a,b   Yao, Gongda ^a,c   Ding, Peijun ^a,d   Fu, Jianming ^a,e   Chen, Ling ^a,d  

^a APPLIED MATERIALS INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c STONY BROOK UNIVERSITY   (United States)

^d STATE UNIVERSITY OF NEW YORK   (United States)

^e PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SELF IONIZED PLASMA (SIP);

AGGLOMERATION; ASPECT RATIO; CHEMICAL MECHANICAL POLISHING; COPPER; CRYSTAL ORIENTATION; FILLER METALS; ION BEAM ASSISTED DEPOSITION; MICROPROCESSOR CHIPS; PHYSICAL VAPOR DEPOSITION; SPUTTER DEPOSITION; TRANSMISSION ELECTRON MICROSCOPY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035336331     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

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8. S M. Rossnagel et al., J. Vac. Sci. Technol. B, Vol. 18, No. 4, 2000, p. 2016.