Failure analysis and stress simulation in small multichip BGAs

IEEE Transactions on Advanced Packaging

Volumn 24, Issue 2, 2001, Pages 216-223

  Moore, Thomas D ^a,b   Jarvis, John L ^c  

^a IEEE   (Ireland)

^b ANALOG DEVICES   (Ireland)

^c UNIVERSITY OF LIMERICK   (Ireland)

Author keywords

BGA; Die attach; Failure analysis; Finite element analysis; Multichip; Solder resist; Thermomechanical stress

Indexed keywords

STRESS SIMULATION;

CHIP SCALE PACKAGES; FAILURE ANALYSIS; FINITE ELEMENT METHOD; RELIABILITY THEORY; SUBSTRATES;

MULTICHIP MODULES;

EID: 0035328922     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.928757     Document Type: Article

References (7)

1. Popcorning in PBGA packages during IR reflow soldering
2. PBGA warpage and stress prediction for efficient creation of the thermomechanical design space for package-level reliability
3. Controlling warpage in BGA packages
4. Improved reliability in small multichip BGAs
5. Numerical analysis of stress singularities in composite materials
6. Mesh design for the p-version of the finite element method