Pad de-embedding in RF CMOS

IEEE Circuits and Devices Magazine

Volumn 17, Issue 3, 2001, Pages 8-11

  Aktas, A ^a   Ismail, M ^a  

^a Ohio State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYZERS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MASKS; SCATTERING PARAMETERS; SUBSTRATES;

DE-EMBEDDING; SYSTEM-ON-CHIP (SOC);

CMOS INTEGRATED CIRCUITS;

EID: 0035328652     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.933786     Document Type: Article

References (7)

1. A fully-integrated single-chip SOC for Bluetooth
2. CMOS technology characterization for analog and RF design
3. On-wafer vector network analyzer calibration and measurements
4. Introduction to bipolar device GHz measurement techniques
5. Layout rules for GHz-probing
6. A new straightforward calibration and correction procedure for on wafer high frequency s-parameter measurements (45 MHz-18 GHz)
7. GHz on-silicon wafer probing calibration methods