A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 8, 1996, Pages 1170-1176

  Chen, Dao Long ^a  

^a Symbios Logic Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION EQUIPMENT; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); PHASE LOCKED LOOPS;

HIGH SPEED SERIAL INTERFACES; RECOVERY CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0030211823     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508265     Document Type: Article

References (16)

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