Design of a multilevel DRAM with adjustable cell capacity

Canadian Journal of Electrical and Computer Engineering

Volumn 26, Issue 2, 2001, Pages 55-59

  Xiang, Yunan ^a   Cockburn, Bruce F ^a   Elliott, Duncan G ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK PARAMETERS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PERMITTIVITY; SEMICONDUCTING SILICON; SPURIOUS SIGNAL NOISE;

CIRCUIT ARCHITECTURE; MULTILEVEL DYNAMIC RANDOM ACCESS MEMORY; STORAGE CAPACITY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035322141     PISSN: 08408688     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. A 16-level/cell dynamic memory
2. An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application
3. Current-mode multivalued dynamic MOS memory with error correction
4. A four-level storage 4-Gb DRAM
5. A comparative simulation study of four multilevel DRAMs
6. Evaluation, design, and implementation of multilevel DRAM
7. A sense and restore technique for multilevel DRAM
8. Design and implementation of a multilevel DRAM