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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E84-A, Issue 4, 2001, Pages 1034-1041

A pipeline chip for quasi arithmetic coding

(1) Wiseman, Yair a,b

a BAR ILAN UNIVERSITY (Israel)

b JERUSALEM COLLEGE OF TECHNOLOGY (Israel)

Author keywords

Compression arithmetic coding; Hardware software combination; Pipeline structure

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; COMPUTER HARDWARE; COMPUTER SOFTWARE; DIGITAL ARITHMETIC; ENCODING (SYMBOLS);

QUASI ARITHMETIC CODING; QUASI ARITHMETIC COMPRESSION ALGORITHMS;

PIPELINE PROCESSING SYSTEMS;

EID: 0035311157 PISSN: 09168508 EISSN: None Source Type: Journal
DOI: None Document Type: Article

Times cited : (27)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.