A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 4, 2001, Pages 696-700

  Sugimoto, Yasuhiro ^a,b  

^a IEEE   (Japan)

^b CHUO UNIVERSITY   (Japan)

Author keywords

CMOS; Current mode circuit; Low voltage; Sample and hold

Indexed keywords

CURRENT MIRROR CIRCUITS; CURRENT MODE CIRCUIT; SAMPLE AND HOLD CIRCUIT;

ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC SWITCHES; MOS DEVICES; SIGNAL TO NOISE RATIO; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0035309922     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.913749     Document Type: Article

References (7)

1. A study of the signal-to-noise ratio of a high-speed current-mode CMOS sample-and-hold circuit
2. A full Nyquist 15-MS/s 8-b differential switched-current A/D converter
3. A switched-current sample-and-hold circuit
4. A current-mode bit-block circuit applicable to low-voltage low-power pipeline video-speed A/D converters
5. A 1.5-V 30-Msps 9- To 10-bit equivalent current-mode CMOS sample-and-hold circuit