Memory operation of InAs quantum dot heterostructure field effect transistor

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 40, Issue 4 B, 2001, Pages 2801-2803

  Son, Heesoo ^a   Kim, Junggun ^a   Kim, Moondeock ^b   Hong, Songcheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

C V measurement; Capacitance; Memory operation; Quantum dot heterostructure FET; Self assembled InAs quantum dot

Indexed keywords

CAPACITANCE MEASUREMENT; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENT MEASUREMENT; ELECTRON TRAPS; GATES (TRANSISTOR); HETEROJUNCTIONS; HYSTERESIS; SELF ASSEMBLY; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR QUANTUM DOTS; SEMICONDUCTOR STORAGE;

CHARGE TRAPPING EFFECTS; MEMORY OPERATIONS;

FIELD EFFECT TRANSISTORS;

EID: 0035300635     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.40.2801     Document Type: Article

References (5)