Modeling of mismatch effect in submicron MOSFETs based on BSIM3 model and parametric tests

IEEE Electron Device Letters

Volumn 22, Issue 3, 2001, Pages 133-135

  Zhang, Q ^b   Liou, J J ^a,b   McMacken, J ^a,c   Thomson, J ^c   Layman, P ^a,c  

^a IEEE   (United States)

^b University of Central Florida   (United States)

^c NOKIA RESEARCH CENTER   (United States)

Author keywords

Analog circuits; BSIM3v3 model; Modeling; MOS transistor mismatch

Indexed keywords

ANALOG CIRCUITS; DRAIN CURRENT; MOS TRANSISTOR MISMATCH;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING;

MOSFET DEVICES;

EID: 0035280113     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.910620     Document Type: Article

References (8)

1. Characterization and modeling of mismatch in MOS transistors for precision analog design
2. Matching properties of MOS transistors
3. Statistical modeling of device mismatch for analog MOS integrated circuits
4. Mismatch characterization of submicron MOS transistors
5. Systematic width-and-length dependent CMOS transistor mismatch characterization and simulation
6. A comprehensive MOSFET mismatch model
7. Measurement of MOS current mismatch in the weak inversion region