Strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Microelectronics Reliability

Volumn 41, Issue 3, 2001, Pages 335-348

  Voldman, S ^a   Anderson, W ^b   Ashton, R ^c   Chaine, M ^d   Duvvury, C ^e   Maloney, T ^f   Worley, E ^g  

^a IBM   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c NOKIA RESEARCH CENTER   (United States)

^d MICRON TECHNOLOGY INC   (United States)

^e TEXAS INSTRUMENTS   (United States)

^f INTEL CORPORATION   (United States)

^g Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0035277904     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00236-5     Document Type: Article

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