An efficient reduction method of a substrate RC network model

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E84-A, Issue 3, 2001, Pages 698-704

  Kimura, Tomohisa ^a   Okumura, Makiko ^b  

^a TOSHIBA CORPORATION   (Japan)

^b KANAGAWA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Circuit simulation; Model reduction; Modeling; Substrate coupling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC ADMITTANCE; MATHEMATICAL MODELS; MATRIX ALGEBRA; POLYNOMIALS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

COUPLING NOISE; MODEL REDUCTION; RESISTOR CAPACITOR NETWORK; SUBSTRATE COUPLING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035274850     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (6)

1. Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's
2. Modeling and analysis of substrate coupling in integrated circuits
3. A simple approach to modeling cross-talk in integrated circuits
4. Addressing substrate coupling in mixed-mode IC's: Simulation and power distribution synthesis
5. Asymptotic waveform evaluation and moment matching for interconnect analysis
6. An extraction of substrate model