Improved neuron MOS-transistor structures for integrated neural network circuits

IEE Proceedings: Circuits, Devices and Systems

Volumn 148, Issue 1, 2001, Pages 25-34

  Rantala, A ^a   Franssila, S ^a   Kaski, K ^a   Lampinen, J ^a   Aberg M ^a   Kuivalainen, P ^a  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; DIGITAL TO ANALOG CONVERSION; GATES (TRANSISTOR); NEURAL NETWORKS; POLYSILICON;

INTEGRATED NEURAL NETWORK CIRCUITS;

MOSFET DEVICES;

EID: 0035247290     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20010055     Document Type: Article

References (12)

1. Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond
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5. A functional MOS transistor featuring gate-level weighted sum and threshold operations
6. Hardware-backpropagation learning of neuron MOS neural networks
7. Neuron MOS binary-logic integrated circuits - Part I: Design fundamentals and soft-hardware-logic circuit implementation
8. Neuron MOS binary-logic integrated circuits - Part II: Simplifying techniques of circuit configuration and their practical applications
9. Neuron MOS voltage-mode circuit technology for multiple-valued logic
10. On the application of the neuron MOS transistor principle for modem VLSI design
11. Impact of high-precision processing on the functional enhancement of neuron-MOS integrated circuits
12. 2