Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 631-634

  Chandar, Subash G ^a   Mehendale, Mahesh ^a   Govindarajan, R ^b  

^a TEXAS INSTRUMENTS   (India)

^b INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; DATA COMPRESSION; DIGITAL SIGNAL PROCESSING; DIGITAL STORAGE;

POWER DISSIPATION;

EMBEDDED SYSTEMS;

EID: 0035213069     PISSN: 10923152     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCAD.2001.968727     Document Type: Article

References (13)

1. Code compression based on operand factorization
2. Code density optimization for embedded DSP processors using data compression techniques
3. Instruction subsetting:Trading power for programmability
4. Compression of embedded system programs
5. Code compression for DSP
6. Code compression for low power embedded system design
7. Arithmetic coding for low power embedded system design
8. Extensions to programmable DSP architectures for reduced power dissipation
9. Executing compressed programs on an embedded RISC architecture