CMOS standard cells characterization for defect based testing

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 384-392

  Pleskacz, Witold A ^a   Kasprowicz, Dominik ^a   Oleszczak, Tomasz ^b   Kuzmicz, Wieslaw ^c  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b Measurement Microsystems A Z Inc   (Canada)

^c ukasiewicz Research Network Institute of Microelectronics and Photonics   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEFECTS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PROBABILITY; VECTORS;

DEFECT BASED TESTING; HIERARCHICAL TEST GENERATION; LOGIC FAULT PROBABILITY;

INTEGRATED CIRCUIT TESTING;

EID: 0035204846     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2001.966792     Document Type: Article

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