Defect-oriented fault simulation and test generation in digital circuits

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 365-371

  Kuzmicz, W ^a   Pleskacz, W ^a   Raik, J ^b   Ubar, R ^b  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENTIAL EQUATIONS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT TESTING; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

ACTIVATION CONDITIONS; DEFECT PROBABILITY; FAULT SIMULATION; FUNCTIONAL FAULT MODEL; HIERARCHICAL FAULT SIMULATION; PHYSICAL DEFECTS; SYSTEM REPRESENTATION; TEST GENERATIONS;

DEFECTS;

EID: 0006805538     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915257     Document Type: Conference Paper

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