Layout manufacturability analysis using rigorous 3-D topography simulation

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2001, Pages 263-266

  Strojwas, A J ^a   Zhu, Z ^a   Ciplickas, D ^a   Li, X ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Etch simulation; Lithography; Manufacturability; OPC; PEB; Topography simulation

Indexed keywords

COMPUTER SIMULATION; MAXWELL EQUATIONS; PHOTOLITHOGRAPHY; PHOTORESISTS; VLSI CIRCUITS;

FOCUS-EXPOSURE MATRIX (FEM) CONDITIONS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035174630     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. METROPOLE-3D: An efficient and rigorous 3D photolithography simulator
2. Modeling of positive photoresist bleaching in optical lithography
3. Efficient and rigorous three-dimensional model for optical lithography simulation
4. New formulation of the Fourier modal method for crossed surface-relief gratings