A 200nV offset 6.5nV/√Hz noise PSD 5.6kHz chopper instrumentation amplifier in 1μm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 362-363+465

  Huang, Q ^a   Menolfi, C ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEMODULATORS; ELECTRIC CLOCKS; ELECTRIC FILTERS; MODULATORS; SPURIOUS SIGNAL NOISE; TRANSISTORS;

COMMON-MODE REJECTION RATIO (CMRR); INSTRUMENTATION AMPLIFIERS;

CHOPPER AMPLIFIERS;

EID: 0035063036     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Circuit techniques for reducing the effects of Op-amp imperfections: Autozeroing, correlated double sampling and chopper stabilization
2. A CMOS nested chopper instrumentation amplifier with 100nV offset
3. A CMOS chopper amplifier
4. A fully integrated CMOS instrumentation amplifier with submicrovolt offset