A 76mm2 8Mb chain ferroelectric memory

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 40-41

  Takashima, D ^a   Takeuchi, Y ^a   Miyakawa, T ^a   Itoh, Y ^a   Ogiwara, R ^a   Kamoshida, M ^a   Hoya, K ^a   Sumiko Mano Doumae, ^a   Ozaki, T ^a   Kanaya, H ^a   Aoki, M ^a   Yamakawa, K ^a   Kunishima, I ^a   Oowaki, Y ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK CODES; CAPACITANCE; CAPACITORS; CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; FERROELECTRIC DEVICES;

FERROELECTRIC CAPACITORS; FERROELECTRIC RANDOM ACCESS STORAGE (FRAM);

RANDOM ACCESS STORAGE;

EID: 0035063026     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. High-density chain ferroelectric random access memory (chain FRAM)
2. A sub-40ns chain FRAM architecture with 7ns cell-plate-line drive