Scheduling coarse-grain operations for VLIW processors

Proceedings of the International Symposium on System Synthesis

Volumn 2000-January, Issue , 2000, Pages 47-53

  Busa N G ^a   Van Der Werf, A ^a   Bekooij, M ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Delay; Digital signal processing; Grain size; Hardware; Laboratories; Processor scheduling; Registers; Synchronization; Telecommunication control; VLIW

Indexed keywords

COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; HARDWARE; INDUCTIVE LOGIC PROGRAMMING (ILP); LABORATORIES; SCHEDULING; SIGNAL PROCESSING; SYNCHRONIZATION; SYNTHESIS (CHEMICAL); TELECOMMUNICATION CONTROL;

DELAY; GRAIN SIZE; PROCESSOR SCHEDULING; REGISTERS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84949958082     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSS.2000.874028     Document Type: Conference Paper

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