Bandpass delta-sigma modulators synthesis with high loop delay

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 344-347

  Yahia, Abdeljalil ^a   Benabes, Philippe ^a   Kielbasa, Richard ^a  

^a SUPELEC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS AND SYNTHESIS; BANDPASS DELTA-SIGMA MODULATOR; CONTINUOUS-TIME BANDPASS; DELTA-SIGMA; DISCRETE TIME; LOOP DELAY; NON IDEALS; RISETIMES;

MODULATORS; DELTA SIGMA MODULATION;

DISCRETE TIME CONTROL SYSTEMS; MODULATORS; SIGNAL TO NOISE RATIO; TRANSFER FUNCTIONS;

BANDPASS DELTA-SIGMA MODULATORS;

EID: 0035019033     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921863     Document Type: Conference Paper

References (10)

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5. th workshop on ADC modeling and testing, September 9-10. 1999-Bordeaux, France.
6. P. Benabes, M. Keramat and R. Kielbasa, "A Methodology for designing continuous-time delta-sigma modulators", European Design and Test Conference, pp. 46-50, Paris, 1997
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8. P. Benabes, P. Aldebert, R. Kielbasa, "A Matlab based tool for bandbass continuous-time delta-sigma modulators design. " In proceedings IEEE International Symposium Circuits & Systems Monterey, CA, 6, pp. 274-277, 1998.
9. P. Benabes, Gauthier and R. Kielbaza, "A multistage closedloop Delta-sigma modulator (MSCL) ", Analog Integrated Circuits and Signal Processing, vol. 11, Number 3, pp. 195-204, November 1996. (Pubitemid 126708269)
10. A. YAHIA, P. Benabes, and R. Kielbaza, "A new technique to compensate the influence of the feedback DAC delay in continuous-time bandpass AZ converters", Appeared at IMTC May 2001.