Modeling and verification of cache coherence protocols

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 5, Issue , 2001, Pages 129-132

  Ivanov, Lubomir ^a   Nunna, Ramakrishna ^b  

^a IONA COLLEGE   (United States)

^b CALIFORNIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE PROTOCOLS; CACHE CONTROLLER; LEVEL-1; MAIN MEMORY; MODELING AND VERIFICATIONS; SERIES-PARALLEL POSET; SET OF RULES; SHARED MEMORY;

CACHE MEMORY; NETWORK PROTOCOLS;

ALGORITHMS; CACHE MEMORY; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ITERATIVE METHODS; MICROPROCESSOR CHIPS;

CACHE COHERENCE PROTOCOLS;

EID: 0035015345     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2001.922002     Document Type: Conference Paper

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