Formal verification: A new partial order approach

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 32-36

  Ivanov, Lubomir ^a   Nunna, Ramakrishna ^b  

^a IONA COLLEGE   (United States)

^b CALIFORNIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED SOFTWARE ENGINEERING; SET THEORY; SYSTEM-ON-CHIP;

FINITE STATE MACHINE SYSTEMS; LARGE SCALE STRUCTURES; OVERALL DESIGN; SERIES-PARALLEL; SERIES-PARALLEL POSET; SYSTEMS ON CHIPS; TEMPORAL VERIFICATION; VERIFICATION METHODOLOGY;

FORMAL VERIFICATION;

EID: 85013325264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806468     Document Type: Conference Paper

References (7)

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3. P. Godcfroid, "Partial Order Methods for the Verification of Concurrent Systems: an Approach to the State Explosion Problem", Doctoral Dissertation, University of Liege, 1994-95
4. R. Naiumasu, G. Gopalakrishnaj], "A New Partial Order Reduction Algorithm for Concurrent System Verification", IFIP, 1996
5. D. Peled, "Combining Partial Order Reductions with On-the-Fly Model Checking", Journal of Formal Methods in Systems Design, 8(0:39-64, 1996
6. S. Bloom, Z. Esik, "Free Shuffle Algebras in Language Varieties", Theoretical Computer Science 163 (1996), 55-89, Elsevier
7. L. lvanov, R. Nunna, S. Bloom, "Modeling and Analysis of Non-Iterated Systems: An Approach based upon Series-Parallel Posets", Procedings of ISCAS'99, Orlando, FL, May 30th - June 2nd 1999