A 10 bit, 50 M sample/s, low power pipelined A/D converter for cable modem applications

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 424-427

  Hamedi Hagh, Sotoudeh ^a   Salama, C A T ^a   Rogers Sr , Edward S ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; CABLE MODEMS; CMOS TECHNOLOGY; CORE AREA; LOW POWER; PIPELINED A/D CONVERTERS; SAMPLING RATES; SUPPLY VOLTAGES;

CABLES; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MODEMS; POLYSILICON; SAMPLING; SPECTRUM ANALYSIS;

MODEMS; ANALOG TO DIGITAL CONVERSION;

CABLE MODEMS;

EID: 0034998878     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921883     Document Type: Conference Paper

References (10)

1. 2", IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, 1997. (Pubitemid 127595815)
2. S. H. Lewis, "Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications", IEEE Transactions on Circuits and Systems II, vol. 39, pp. 516-523, 1992.
3. A. M. Abo, and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter", IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, 1999.
4. D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., Toronto, 1997.
5. A. Yukawa, "A CMOS 8-Bit High-Speed A/D Converter IC", IEEE J. Solid-State Circuits, vol. sc-20, pp. 775-779, 1998.
6. B. Song, M. F. Tompsett, and K. R. Lakshmikuma, "A 12-bit 1-Msample/s Capacitor Error-Averaging Pipelined A/D converter", IEEE J. Solid-State Circuits, vol. 23, No. 6, pp. 1324-1333, 1988.
7. H. Recoules, R. Bouchakour, P. Loumeau, F. T. Braz, "Two SC-CMFB Networks Used in Fully Differential OTA: Measurements and Improvements", Midwest Symposium on Circuits and Systems, pp. 352-355, 1999.
8. M. Afghahi, J. Yuan, "Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits", IEEE J. Solid-State Circuits, vol. 26, pp. 1168-1170, 1991. (Pubitemid 21690751)
9. T. B. Cho, P. R. Gray, "A 10 b, 20 Msample/s, 35 mW Pipelined A/D Converter", IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, 1995.
10. A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A Scalable Substrate Noise Coupling Model for Design of Mixed-Signal IC's", IEEE J. Solid-State Circuits, vol. 35, pp. 895-904, 2000.