RT-level fault simulation based on symbolic propagation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 240-245

  Sinanoglu, O ^a   Orailoglu, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; FAILURE ANALYSIS; GATES (TRANSISTOR); VLSI CIRCUITS;

FAULT SIMULATION; REGISTER TRANSFER LEVEL; SYMBOLIC PROPAGATION;

INTEGRATED CIRCUIT TESTING;

EID: 0034995121     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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