A neuroevolution method for dynamic resource allocation on a chip multiprocessor

Proceedings of the International Joint Conference on Neural Networks

Volumn 4, Issue , 2001, Pages 2355-2360

  Gomez, F J ^a   Burger, D ^a   Miikkulainen, R ^a  

^a University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; DYNAMIC PROGRAMMING; GENETIC ALGORITHMS; LEARNING ALGORITHMS; MICROPROCESSOR CHIPS; MULTILAYER NEURAL NETWORKS; RESOURCE ALLOCATION;

DYNAMIC RESOURCE ALLOCATION; ENFORCED SUBPOPULATIONS ALGORITHM; STATIC CACHE PARTITIONING;

RECURRENT NEURAL NETWORKS;

EID: 0034873222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Clock rate versus IPC: The end of the road for conventional microarchitectures
2. Piranha: A scalable architecture based on single-chip multiprocessing
3. The simplescalar tool set version 2.0
4. Power4 focuses on memory bandwidth
5. Incremental evolution of complex general behavior
6. Solving non-Markovian control tasks with neuroevolution
7. A review of evolutionary artificial neural networks