A new approach to characterize substrate losses of on-chip inductors

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2001, Pages 115-118

  Schimpf, K ^a   Benna, B ^a   Proetel, D ^a  

^a Texas Instruments Deutschland GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC INDUCTORS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT TESTING; RESISTORS; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES;

DEEMBEDDING PROCESS; ON-CHIP INDUCTORS; PARAMETER EXTRACTION; SUBSTRATE LOSSES;

MICROELECTRONIC PROCESSING;

EID: 0034868047     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. An investigation of on-chip spiral inductors on a 0.6um BICMOS technology
2. Monolithic spiral inductors fabricated using a VLSI Cu-Damascene interconnect technology and low-loss substrates
3. Easy simulation and design of on-chip inductors in standard CMOS processes
4. Accurate design of inductors on multi-chip moduleusing high-resistivity silicon substrate
5. Spiral inductor substrate loss modelling in silicon RFICs