Monolithic Spiral Inductors Fabricated Using a VLSI Cu-Damascene Interconnect Technology and Low-Loss Substrates

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 99-102

  Burghartz, J N ^a   Edelstein, D C ^a   Jenkins, K A ^a   Jahnes, C ^a   Uzoh, C ^a   O'Sullivan, E J ^a   Chan, K K ^a   Soyuer, M ^a   Roper, P ^a   Cordes, S ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC INDUCTORS; INTEGRATED CIRCUIT INTERCONNECTS; SAPPHIRE; SUBSTRATES; CHEMICAL POLISHING; COPPER; DRY ETCHING; LITHOGRAPHY; OPTIMIZATION; OXIDES; SEMICONDUCTING SILICON; SILICON ON SAPPHIRE TECHNOLOGY; VLSI CIRCUITS;

CU DAMASCENE; CU DAMASCENE INTERCONNECTS; HIGH-RESISTIVITY SILICON SUBSTRATE; INDUCTOR STRUCTURES; INTERCONNECT TECHNOLOGY; LOW-LOSS SUBSTRATES; MONOLITHICS; SAPPHIRE SUBSTRATES; SPIRAL INDUCTOR; VLSI INTERCONNECTS;

VLSI CIRCUITS; ELECTRIC INDUCTORS;

CHEMICAL MECHANICAL POLISHING; DAMASCENE PROCESS; ELECTROLESS CAPPING; HIGH RESISTIVITY SILICON; MONOLITHIC SPIRAL INDUCTION; VLSI INTERCONNECT TECHNOLOGY;

EID: 0030407071     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553131     Document Type: Conference Paper

References (4)

1. J.N.Burghartz et al., Techn. Dig. IEDM, 1995, pp. 1015-1017.
2. K.B.Ashby et al., Proc. BCTM, 1994, pp. 179-182.
3. D.C.Edelstein, Proc. 10th Int. VLSI Multi-Level Interconn. Conf., 1995, pp. 301-307.
4. J.N.Burghartz et al., Roc. BCTM, 1996, to be published.