High-speed bit-parallel systolic multipliers for a class of GF(2m)

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 291-294

  Lee, C Y ^a   Lu, E H ^a   Jau Yien, ^a  

^a CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; POLYNOMIALS; SYSTOLIC ARRAYS;

SYSTOLIC MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0034857798     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Discrete logarithms in finite fields and their cryptographic significance
2. New directions in cryptography
3. m)
4. m)
5. m)
6. Systolic dual basis serial multiplier
7. m)
8. m)
9. Low complexity bit-parallel canonical and normal basis multipliers for a class of finite fields
10. Low-complexity bit-parallel multipliers for a class of finite fields
11. New low-complexity bit-parallel finite field multipliers using weakly dual bases
12. m) yielding small complexity arithmetic