A dynamically reconfigurable architecture for embedded systems

Proceedings of the International Workshop on Rapid System Prototyping

Volumn , Issue , 2001, Pages 32-37

  Sassatelli, G ^a   Cambon, G ^a   Galy, J ^a   Torres, L ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CODE DIVISION MULTIPLE ACCESS; COMPUTER ARCHITECTURE; DATA PROCESSING; INTERNET; MOBILE TELECOMMUNICATION SYSTEMS; MULTIMEDIA SYSTEMS; NETWORK PROTOCOLS; PERSONAL COMPUTERS;

DATA BANDWIDTH; MOTION ESTIMATION ALGORITHMS;

EMBEDDED SYSTEMS;

EID: 0034857530     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Architecture of FPGAs and CPLDs: A tutorial
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6. VLSI architecture for block-matching motion estimation algorithm
7. Discrete cosine transform
8. A Re-configurable VLSI coprocessing system for the block matching algorithm