Logic minimization using exclusive OR gates

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 115-120

  Ciriani, V ^a  

^a UNIVERSITY OF PISA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; BOOLEAN FUNCTIONS; DATA STRUCTURES; OPTIMIZATION;

SUM OF PSEUDO-PRODUCT (SPP) FORMS;

LOGIC GATES;

EID: 0034846648     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378361     Document Type: Conference Paper

References (10)

1. Doing two-level logic minimization 100 times faster
2. A heuristic algorithm to design AND-OR-EXOR three-Llevel networks
3. AOXMIN-MV: A heuristic algorithm for AND-OR-XOR minimization
4. On a new boolean function with applications
5. Three-level decomposition with application to PLDs
6. Espresso-Signature: A new exact minimizer for logic functions