Wafer rework strategies at the photolithography stage

International Journal of Industrial Engineering : Theory Applications and Practice

Volumn 8, Issue 2, 2001, Pages 122-130

  Sha, D Y ^a   Hsieh, L ^a   Chen, K ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Child lot; Cycle time; Mother lot; Rework strategy; Simulation; Utilization

Indexed keywords

COMPETITION; COMPUTER SIMULATION; COST BENEFIT ANALYSIS; MACHINERY; PRODUCTION CONTROL; PRODUCTIVITY; SCHEDULING; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

CHILD LOT; CYCLE TIME; MOTHER LOT; REWORK STRATEGY; UTILIZATION;

PHOTOLITHOGRAPHY;

EID: 0034838789     PISSN: 10724761     EISSN: 1943670X     Source Type: Journal    
DOI: None     Document Type: Article

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