Borderless contact leakage induced standby current failure on sub-0.15um CMOS device

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2001, Pages 165-168

  Kim, D H ^a   Kim, J H ^a   Hwang, B J ^a   Cho, D Y ^a   Kim, K C ^a   Kim, S B ^a   Hong, J I ^a   Park, J W ^a   Lee, M Y ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC CONTACTS; ELECTRIC POTENTIAL; FAILURE ANALYSIS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS; LITHOGRAPHY; SCHEMATIC DIAGRAMS; STATIC RANDOM ACCESS STORAGE;

BORDERLESS CONTACT LEAKAGE; INTERLAYER DIELECTRIC THICKNESS; SHALLOW TRENCH ISOLATION; STANDBY CURRENT FAILURE;

CMOS INTEGRATED CIRCUITS;

EID: 0034834138     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A novel, borderless metal-to-diffusion contact technique
2. A novel borderless contact interconnect technology using aluminum oxide etch stop for high performance SRAM and logic
3. A new and improved borderless contact structure for high-performance Ti-Salicide in sub-quarter micron CMOS device