Robustness of LDMOS power transistors in SOI-BCD processes and derivation of design rules using thermal simulation

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2001, Pages 157-160

  Krabbenborg, B H ^a   Van der Pol, J A ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

BCD; DMOS; High voltage; Safe operating area; Silicon on insulator; Smart power; Thermal simulation

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; FAILURE ANALYSIS; ROBUSTNESS (CONTROL SYSTEMS); SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE MEASUREMENT; THERMAL EFFECTS;

POWER TRANSISTORS; SAFE OPERATING AREA (SOA);

MOSFET DEVICES;

EID: 0034830048     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)