A novel FPGA architecture supporting wide shallow memories

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 75-78

  Oldridge, S W ^a   Wilton, S J E ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; INTEGRATED CIRCUITS; RANDOM ACCESS STORAGE;

ON-CHIP MEMORY; ON-CHIP USER STORAGE; SHALLOW MEMORY; SWITCH BLOCKS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034827310     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. The memory/logic interface in FPGA's with large embedded memory arrays
2. Architecture and algorithms for field-programmable gate arrays with embedded memory
3. HSRA: High-speed, hierarchical synchronous reconfigurable array