Correlated double sampling integrator insensitive to parasitic capacitance

Electronics Letters

Volumn 37, Issue 3, 2001, Pages 151-153

  Kajita, T ^a   Temes, G C ^a   Moon, U K ^a  

^a OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; ELECTRIC CHARGE; OPERATIONAL AMPLIFIERS; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS;

CORRELATED DOUBLE SAMPLING (CDS) SCHEME;

DIGITAL INTEGRATED CIRCUITS;

EID: 0034826264     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010130     Document Type: Article

References (5)

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2. KAJITA, T., MOON, U.-K., and TEMES, G.C.: 'A noise-shaping accelerometer interface circuit for two-chip implementation'. IEEE ISCAS 2000, May 2000, pp. IV-337-IV-340
3. STEENSGAARD, J.: 'Clocking scheme for switched-capacitor circuits'. IEEE ISCAS 1998, 1998, pp. I-488-I-491
4. HAUG, K., TEMES, G.C., and MARTIN, K.: 'Improved offset-compensation schemes for switched-capacitor circuits'. IEEE ISCAS 1984, 1984, pp. 1054-1057
5. NAGARAJ, K., VLACH, J., VISWANATHAN, T.R., and SINGHAL, K.: 'Switched-capacitor integrator with reduced sensitivity to amplifier gain', Electron. Lett., 1986, 22, pp. 1103-1105