Plasma processing of high density vias in compliant wafer level package

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4428, Issue , 2001, Pages 285-291

  Li, Y ^a   Patel, C S ^a   Hess, D ^a   Martin, K ^a   Meindl, J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

High density vias; Plasma process; Wafer level package

Indexed keywords

EPOXY RESINS; ETCHING; METHANE; OXIDES; PLASMA DENSITY; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PLASTIC FILMS; SILICA; SILICON; STRUCTURE (COMPOSITION);

CHAMBER PRESSURE; COMPLIANT WAFER LEVEL PACKAGE; HIGH DENSITY VIAS; POLYNORBORNENE FILMS;

ELECTRONICS PACKAGING;

EID: 0034823010     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. New chip scale package with CTE matching to the board
2. Critical issues with chip scale packages
3. Low cost high density compliant wafer level package
4. Novel photosensitive dielectric materials based on polynorbornene for wafer level packaging applications
5. Plasma etching of polymer dielectric films for electronics packaging
6. Processing and microwave characterization of multilevel interconnects using benzocyclobutene dielectric
7. Effects of oxygen and fluorine on the dry etch characteristics of organic low-k dielectrics