Retargetable compilation for low power

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2001, Pages 254-259

  Shiue, W T ^a  

^a Silicon Metrics Corporation   (United States)

Author keywords

Architecture aware compiler design; High performance and low power design; Instruction scheduling; Register allocation

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; LOGIC DESIGN; STORAGE ALLOCATION (COMPUTER);

MULTIPLE DATA MEMORY BANKS;

PROGRAM COMPILERS;

EID: 0034820546     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/371636.371750     Document Type: Conference Paper

References (11)

1. Software synthesis and code generation for signal processing systems
2. Efficient instruction scheduling for a pipelined processor
3. Register allocation via coloring
4. Improvement to graph coloring register allocation
5. Simultaneous reference allocation in code generation for dual data memory bank ASIPs
6. Register allocation and binding for low power
7. Power analysis and minimization technique for embedded DSP software