A regularity-driven fast gridless detailed router for high frequency datapath designs

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2001, Pages 130-135

  Das, S ^a   Khatri, S P ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; DATA FLOW ANALYSIS; DATA STRUCTURES; LOGIC CIRCUITS; MICROPROCESSOR CHIPS;

DATAPATH LAYOUTS;

ROUTERS;

EID: 0034818886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/369691.369752     Document Type: Conference Paper

References (10)

1. Layout synthesis for datapath designs
2. Data path placement with regularity
3. A timing-driven data path layout synthesis with integer programming
4. Datapath routing based on a decongestion metric
5. A signature based approach to regularity extraction
6. Regularity extraction via clan-based structural circuit decomposition
7. An algorithm for path connections and its applications
8. An improvement in printed circuit board routability using a maze-running algorithm
9. Pattern router
10. Parametric pattern router